@conference {17998,
	title = {An area-efficient high-throughput hybrid interconnection network for single-chip parallel processing},
	booktitle = {Proceedings of the 45th annual Design Automation Conference},
	series = {DAC {\textquoteright}08},
	year = {2008},
	month = {2008///},
	pages = {435 - 440},
	publisher = {ACM},
	organization = {ACM},
	address = {New York, NY, USA},
	abstract = {Single-chip parallel processing requires high bandwidth between processors and on-chip memory modules. A recently proposed Mesh-of-Trees (MoT) network provides high throughput and low latency at relatively high area cost. In this paper, we introduce a hybrid MoT-BF network that combines MoT network with the area efficient butterfly network. We prove that the hybrid network reduces MoT network{\textquoteright}s area cost. Cycle-accurate simulation and post-layout results all show that significant area reduction can be achieved with negligible performance degradation, when operating at same clock rate.},
	keywords = {hybrid networks, mesh-of-trees, on-chip networks},
	isbn = {978-1-60558-115-6},
	doi = {10.1145/1391469.1391583},
	url = {http://doi.acm.org/10.1145/1391469.1391583},
	author = {Balkan,Aydin O. and Gang Qu and Vishkin, Uzi}
}
